Building a Custom PWM DC Motor Controller: H-Bridge Design & Thermals
Building the power stage now? IR2110 Gate Driver IC on Amazon.in → | IRF3205 MOSFET (55V 110A) →
If you have ever built a mid-to-high-power robotic system, chances are you started with off-the-shelf motor driver modules. But as soon as you push beyond simple desktop toys into high-torque actuators, those generic modules quickly reveal their limitations.
Modules built around legacy chips like the L298N rely on bipolar junction transistors (BJTs) with massive internal collector-emitter voltage drops ($V_{CE(\text{sat})} \approx 1.8\text{V}$ to $2.5\text{V}$). At $2\text{ A}$ of load, the driver wastes nearly $5\text{ W}$ of power as pure heat, requiring bulky heatsinks just to keep from thermal throttling. Cheap drivers also cap switching frequencies below $10\text{ kHz}$, forcing your motor windings to emit an annoying, high-pitched acoustic whine during operation.
To achieve high efficiency, silent operation ($>20\text{ kHz}$ ultrasonic switching), and compact thermal footprints, you must build a custom N-Channel MOSFET H-Bridge.
Here is an end-to-end engineering breakdown of how to design a high-performance DC motor controller from scratch — covering topology selection, gate driver bootstrapping, thermal dissipation math, transient snubbing, and bare-metal dead-time firmware.
1. H-Bridge Topology: The 4 N-Channel Standard
An H-Bridge topology allows a DC motor to run forward, reverse, or brake by selectively closing diagonal pairs of four electronic switches ($Q_1, Q_2, Q_3, Q_4$).
Why 4 N-Channel MOSFETs?
While using P-Channel MOSFETs on the high side simplifies gate drive circuitry (since pulling the gate to ground turns them ON), P-Channel silicon has roughly $2.5\times$ higher on-resistance ($R_{DS(\text{on})}$) than N-Channel devices of equivalent die size due to lower hole mobility in silicon.
To minimize $I^2R$ conduction losses, high-power drivers use 4 N-Channel MOSFETs. However, this introduces a classic chicken-and-egg problem:
To fully turn ON an N-Channel MOSFET on the high side ($Q_1$ or $Q_3$), its gate-to-source voltage $V_{GS}$ must sit $10\text{V}$ to $15\text{V}$ above its source pin. But when $Q_1$ turns ON, its source pin rises to $+V_{\text{BUS}}$ (e.g., $24\text{V}$). This means the high-side gate driver must supply $24\text{V} + 10\text{V} = 34\text{V}$ to keep the upper switch fully saturated!
High-Side Bootstrapping Logic
To generate this elevated gate voltage without an expensive isolated power supply, we use a dedicated gate driver IC (such as the IR2110 or EG2104) configured with a bootstrap circuit:
- Charging Phase: When the low-side MOSFET ($Q_2$) turns ON, the high-side source pin $V_{VS}$ is pulled down to Ground. Current flows from the $+12\text{V}$ supply through the fast-recovery bootstrap diode ($D_{\text{boot}}$) to charge the bootstrap capacitor ($C_{\text{boot}}$) up to $\sim 12\text{V}$.
- Discharging / High-Side Drive Phase: When $Q_2$ turns OFF and the high-side MOSFET ($Q_1$) turns ON, $V_{VS}$ rises to $+V_{\text{BUS}}$. The charged capacitor $C_{\text{boot}}$ rides up on top of $V_{\text{BUS}}$, boosting the high-side gate supply voltage $V_{VB}$ up to $V_{\text{BUS}} + 12\text{V}$.
IR2110 High and Low Side Gate Driver IC — the industry-standard bootstrap gate driver for exactly this topology. Handles up to 500V offset with built-in shoot-through protection logic.
Check Price on Amazon.in →
2. Preventing Shoot-Through with Hardware Dead-Time
The most lethal failure mode in H-Bridge design is Shoot-Through. If $Q_1$ (High Side) and $Q_2$ (Low Side) on the same leg turn ON simultaneously even for a few nanoseconds, $+V_{\text{BUS}}$ is shorted directly to Ground through the low-resistance MOSFET channels. This causes instantaneous current spikes, overheating, and catastrophic silicon package failure.
Because MOSFET turn-off times ($t_{\text{off}}$) are generally longer than turn-on times ($t_{\text{on}}$) due to gate-charge discharge delays, software must explicitly insert a Dead-Time interval (typically $200\text{ ns}$ to $1\mu\text{s}$) where both switches on a leg are forced OFF before turning ON the complementary switch.
3. Thermal Dissipation & Power Calculations
To size heatsinks and select the right MOSFET package, we must compute two distinct sources of power loss: Conduction Loss and Switching Loss.
A. Conduction Loss ($P_{\text{cond}}$)
Conduction loss occurs while the MOSFET is fully turned ON, acting like a small resistor $R_{DS(\text{on})}$. For two conducting MOSFETs in the current path (one high-side, one low-side) operating at a duty cycle $D$:
$$P_{\text{cond}} = 2 \cdot I_{\text{RMS}}^2 \cdot R_{DS(\text{on})}$$
B. Switching Loss ($P_{\text{sw}}$)
Every time a MOSFET transitions between ON and OFF states, it passes through a linear region where both drain-source voltage ($V_{DS}$) and channel current ($I_D$) are non-zero. At high switching frequencies ($f_{\text{sw}} = 20\text{ kHz}$), these transitions dominate thermal generation:
$$P_{\text{sw}} = V_{\text{BUS}} \cdot I_{\text{load}} \cdot (t_r + t_f) \cdot f_{\text{sw}}$$
Where $t_r$ and $t_f$ are the rise and fall times of the MOSFET channel (determined by gate drive current capability).
C. Total Thermal Resistance Equation
Once total power loss $P_{\text{total}} = P_{\text{cond}} + P_{\text{sw}}$ per MOSFET is calculated, we determine the final silicon junction temperature ($T_J$):
$$T_J = T_A + P_{\text{total}} \cdot (\theta_{JC} + \theta_{CS} + \theta_{SA})$$
Where:
- $T_A$ = Ambient Room Temperature (e.g., $30^\circ\text{C}$)
- $\theta_{JC}$ = Junction-to-Case Thermal Resistance ($^\circ$C/W)
- $\theta_{CS}$ = Case-to-Heatsink Interface Thermal Resistance ($^\circ$C/W)
- $\theta_{SA}$ = Heatsink-to-Ambient Thermal Resistance ($^\circ$C/W)
Numerical Design Example
Let's evaluate a single MOSFET operating under real bench conditions: $V_{\text{BUS}} = 24\text{V}$, $I_{\text{load}} = 15\text{A}$, $f_{\text{sw}} = 20\text{ kHz}$, using an IRF3205 in TO-220 ($R_{DS(\text{on})} = 8\text{ m}\Omega$, $t_r = 60\text{ ns}$, $t_f = 45\text{ ns}$, $\theta_{JC} = 1.0\,^\circ$C/W).
| Step | Calculation | Result |
|---|---|---|
| Conduction Loss | $(15\text{A})^2 \cdot 0.008\,\Omega$ | 1.8 W |
| Switching Loss | $24\text{V} \cdot 15\text{A} \cdot (60\text{ns}+45\text{ns}) \cdot 20{,}000\text{Hz}$ | 0.756 W |
| Total Power / Switch | 1.8 W + 0.756 W | 2.556 W |
| TJ — no heatsink ($\theta_{JA}=62$) | $30^\circ\text{C} + (2.556\text{W} \cdot 62)$ | 188.5°C — destroyed (max 175°C) |
| TJ — small heatsink ($\theta_{SA}=12,\theta_{CS}=0.5$) | $30^\circ\text{C} + (2.556\text{W} \cdot 13.5)$ | 64.5°C — rock solid |
4. Overshoot Protection & RC Snubber Networks
A DC motor is a massive inductor. When a MOSFET switches OFF rapidly, the energy stored in the magnetic field ($E = \frac{1}{2} L I^2$) cannot instantly drop to zero. It attempts to maintain current flow, creating an inductive voltage spike ($V = L \cdot \frac{di}{dt}$) that rings aggressively across $V_{DS}$.
To damp this high-frequency ringing and protect the MOSFET body diodes from avalanche breakdown:
- RC Snubber Network: Placed in parallel across the Drain and Source pins of each MOSFET.
- Typical Snubber Resistor ($R_s$): $10\,\Omega$ to $47\,\Omega$ (carbon composition or non-inductive film).
- Typical Snubber Capacitor ($C_s$): $1\text{ nF}$ to $10\text{ nF}$ (100V ceramic disc).
- Bulk Low-ESR Decoupling Capacitors: Place a matrix of $1000\mu\text{F}$ electrolytic caps in parallel with $1\mu\text{F}$ ceramic caps as close as physically possible to the high-side Drain pins to absorb high-frequency bus ripple.
- Transient Voltage Suppressor (TVS) Diodes: A bidirectional TVS diode (e.g., SMCJ30A) across the motor terminals clamps back-EMF spikes safely below the MOSFET's max $V_{DS}$ rating.
SMCJ30CA Bidirectional TVS Diodes (10-pack) — cheap insurance against back-EMF spikes destroying your MOSFETs. Solder one across every motor terminal pair.
Check Price on Amazon.in →
5. Bare-Metal Firmware: Hardware Timers & Dead-Time Insertion
To drive an H-Bridge cleanly at $20\text{ kHz}$, you should never use software delay routines or simple analogWrite() wrappers. You must configure the microcontroller's hardware timer peripheral to generate Center-Aligned Complementary PWM with Hardware Dead-Time Insertion.
Here's an STM32 (ARM Cortex-M, HAL-based) timer configuration that sets up TIM1 for center-aligned complementary PWM with a hardware-inserted dead-time — the dead-time here is enforced entirely by the timer's break-and-dead-time register, so it holds even if your main loop stalls:
hbridge_pwm_init.c · c
#include "stm32f4xx_hal.h"
TIM_HandleTypeDef htim1;
void HBridge_PWM_Init(void) {
TIM_OC_InitTypeDef sConfigOC = {0};
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
htim1.Instance = TIM1;
htim1.Init.Prescaler = 0;
htim1.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1; // center-aligned
htim1.Init.Period = 2100 - 1; // 20 kHz @ 84 MHz
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim1.Init.RepetitionCounter = 0;
HAL_TIM_PWM_Init(&htim1);
sConfigOC.OCMode = TIM_OCMODE_PWM1;
sConfigOC.Pulse = 1050; // 50% duty (example)
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCNPolarity= TIM_OCNPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1);
// Hardware dead-time: enforced by silicon, immune to software hangs
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_ENABLE;
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_ENABLE;
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
sBreakDeadTimeConfig.DeadTime = 42; // ~500 ns @ 84 MHz timer clock
sBreakDeadTimeConfig.BreakState = TIM_BREAK_ENABLE;
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig);
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); // Q1 (high side)
HAL_TIMEx_PWMN_Start(&htim1, TIM_CHANNEL_1); // Q2 (low side, complementary)
}
This complementary timer setup guarantees that high-side and low-side gate signals are locked in hardware sync. Even if the main loop hangs or experiences software delays, the hardware timer will never allow the two gate lines to overlap, protecting your physical board from shoot-through damage.
This robust driver interface connects cleanly with the real-time execution architectures documented in Safe, Lock-Free State Machines in Rust for Multi-Axis Robotic Articulation, and helps prevent the thermal and latency bugs detailed in the Sim-to-Real Control Loop Post-Mortem.
6. Hardware Bench & Component Sourcing Directory
If you are laying out a custom PCB or prototyping a high-frequency H-Bridge on a breadboard, here are the essential components:
1. Gate Driver ICs & Power MOSFETs
- Gate Driver ICs: the industry-standard IR2110 High and Low Side Gate Driver IC, or the compact EG2104 Half-Bridge Gate Driver Module for bootstrap high-side switching.
- Power MOSFETs: low $R_{DS(\text{on})}$ switches like the IRF3205 N-Channel Power MOSFET (55V 110A) or the IRFZ44N N-Channel Power MOSFET.
2. Circuit Protection & Passive Components
- Bulk & Snubber Capacitors: filter high-frequency bus ripple using Low-ESR Electrolytic Capacitors (1000µF, 35V/50V) alongside 100nF Ceramic Disc Capacitors.
- Transient Suppression: protect your silicon from inductive kickback using bidirectional TVS Diodes (SMCJ series) and high-speed UF4007 Ultra-Fast Recovery Diodes for the bootstrap network.
KAIWEETS HT118A Digital Multimeter with NCV — useful for verifying $R_{DS(\text{on})}$, bootstrap capacitor charge, and dead-time gaps on the bench before powering up a 24V bus.
Check Price on Amazon.in →
Conclusion: Total Control Over Your Power Stage
Designing a custom N-Channel MOSFET H-Bridge requires careful attention to both electrical and physical details — from sizing bootstrap capacitors to calculating thermal dissipation and configuring hardware dead-time timers. By moving away from legacy drivers like the L298N and building a tailored 20 kHz power stage, you gain total control over your actuator hardware: eliminating audible motor whine, maximizing power efficiency, and protecting your systems from thermal and overvoltage faults.
Explore more on Embedded Systems, Control Systems, and Robotics to keep building out your power electronics stack.
Disclosure: This post contains affiliate links. If you make a purchase through them, AppliedKaos may earn a small commission at no extra cost to you. All recommendations are based on genuine use and opinion.
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