Synthesizing SystemVerilog with Yosys on WSL

 

From Code to Gates: Synthesizing SystemVerilog with Yosys on WSL

Welcome back to AppliedKaos! In our previous guide, we dipped our toes into the world of low-latency FPGA design by writing and simulating a SystemVerilog glitch filter using Icarus Verilog and GTKWave.

Simulation is great for proving your logic works in a perfect, virtual environment. But an FPGA isn't a virtual machine—it's physical silicon.

Today, we take the crucial next step: Synthesis. We are going to transform our human-readable SystemVerilog code into a netlist of actual digital hardware components (logic gates, multiplexers, and flip-flops) using Yosys, the powerhouse of the open-source FPGA toolchain.

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What is Logic Synthesis?

If Icarus Verilog is a "debugger," Yosys is the "compiler."

In the software world, a compiler translates C++ or Python into machine code (1s and 0s) that a CPU executes sequentially. In the hardware world, a synthesizer translates Hardware Description Language (HDL) into a netlist.

A netlist is exactly what it sounds like: a list of electronic components (nets) and the wires connecting them. Yosys analyzes your always_ff blocks and if/else statements and figures out exactly how to wire up hardware registers and logic gates to execute your behavior with absolute, deterministic latency.

The Two Stages of Synthesis

1. Generic Synthesis: Converting your SystemVerilog into generic logic gates (AND, OR, NOT) and D-Type Flip-Flops.

2. Technology Mapping: Converting those generic gates into the specific physical resources (Look-Up Tables, or LUTs) available on your target FPGA chip (like a Lattice iCE40 or Xilinx Artix-7).

Today, we will focus on generic synthesis to visualize the hardware we've created!

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Step-by-Step Instructions: Synthesizing with Yosys

We will be continuing in the same WSL Ubuntu 22.04 environment we set up in Part 1. Ensure your OSS CAD Suite is still in your system path.

Step 1: Install Graphviz for Visualization

To actually see the hardware schematic Yosys generates, we need a graphing tool called Graphviz. Open your WSL terminal and install it:

Bash

sudo apt update
sudo apt install -y graphviz

Step 2: Create the Yosys Script

Navigate back to your project directory:

Bash

cd ~/kaos_fpga_filter

While you can run Yosys interactively, it’s best practice to use a script. Create a file named synth.ys:

Code snippet

# synth.ys - AppliedKaos Yosys Synthesis Script

# 1. Read the SystemVerilog design file
read_verilog -sv glitch_filter.sv

# 2. Check the design hierarchy and set the top module
hierarchy -check -top glitch_filter

# 3. Perform generic synthesis 
# (We use 'prep' instead of 'synth' here to keep the schematic readable and generic, 
# rather than mapping it to a highly optimized, hard-to-read specific FPGA architecture just yet)
prep -top glitch_filter

# 4. Clean up unused signals and optimize
clean

# 5. Output a visual schematic of our hardware (generates an SVG file)
show -format svg -prefix glitch_filter_schematic

# 6. Write the generic netlist to a JSON file (useful for later stages)
write_json glitch_filter_netlist.json

Step 3: Run the Synthesis

Execute Yosys and pass it your script. In your terminal, run:

Bash

yosys synth.ys

You will see a massive wall of text fly by. This is Yosys working its magic! It’s analyzing the logic, optimizing away dead code, identifying your THRESHOLD parameter, and constructing the circuit graph.

Look for a message near the end that says Output filename: glitch_filter_schematic.svg. If you see that, synthesis was successful!

Step 4: View Your Hardware Schematic

Because we are on WSL, viewing the SVG file directly from the terminal can be tricky without an X-Server. The easiest way to view it is to open the file in your Windows web browser.

From your WSL terminal, you can launch it using Windows Explorer:

Bash

explorer.exe glitch_filter_schematic.svg

(Alternatively, you can copy the .svg file to your /mnt/c/Users/YourName/Desktop directory and open it normally).

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Understanding the Yosys Output

When you open the SVG, you are looking at the actual hardware architecture of your glitch filter! You should be able to identify a few key structures:

• D-Type Flip-Flops ($dff): These represent our counter, clean_out, and sampling registers. They are the memory elements synchronized to the clk signal.

• Multiplexers ($mux): These are the hardware representation of your if/else statements. They choose which data path routes to the registers based on whether the input matches the output.

• Adders ($add): You will see a block representing the counter <= counter + 1'b1; logic.

• Comparators ($eq, $ge): These represent the logic checking if the counter has reached the THRESHOLD.

By keeping our logic shallow (minimizing the number of gates between flip-flops), we ensure that the electrical signals can propagate through this entire schematic within a single clock cycle, maintaining that sweet, sweet ultra-low latency.

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Conclusion

You’ve successfully transitioned from writing abstract code to generating a concrete hardware schematic using entirely open-source tools. You can now visually prove that your SystemVerilog translates into a clean, predictable circuit.

Simulation proves your logic is correct. Synthesis proves your logic is buildable. The next step to FPGA design flow is place and route on the board !

Stay Kaotic!

 The AppliedKaos Team