From Netlist to Silicon: Place and Route with NextPNR on WSL
From Netlist to Silicon: Place and Route with NextPNR on WSL Welcome back to the final installment of our AppliedKaos beginner series on low-latency FPGA design! In Part 1, we wrote and simulated a SystemVerilog glitch filter. In Part 2, we used Yosys to synthesize that code into a generic hardware netlist—proving our logic was physically buildable. Today, we cross the finish line. We are going to take that generic netlist, map it to a specific physical FPGA chip, and generate the final binary file (the bitstream ) that makes the hardware tick. To do this, we’ll use NextPNR and the Project IceStorm tools, remaining entirely within our open-source WSL Ubuntu 22.04 ecosystem. The Final Hurdles: PnR and Bitstreams Before we dive into the commands, let's clarify what is actually happening in this final stage. What is Place and Route (PnR)? Yosys gave us a netlist of logic gates and flip-flops, but it didn't tell us where those components should physically sit on the FPGA die...